A1

CHCHK*

Channel check

A2

SD7

System data bus (bit 7)

A3

SD6

System data bus (bit 6)

A4

SD5

System data bus (bit 5)

A5

SD4

System data bus (bit 4)

A6

SD3

System data bus (bit 3)

A7

SD2

System data bus (bit 2)

A8

SD1

System data bus (bit 1)

A9

SD0

System data bus (bit 0)

A10

IOCHRDY

System I/O channel ready

A11

AEN

Address enable

A12

SA19

System address bus (bit 19)

A13

SA18

System address bus (bit 18)

A14

SA17

System address bus (bit 17)

A15

SA16

System address bus (bit 16)

A16

SA15

System address bus (bit 15)

A17

SA14

System address bus (bit 14)

A18

SA13

System address bus (bit 13)

A19

SA12

System address bus (bit 12)

A20

SA11

System address bus (bit 11)

A21

SA10

System address bus (bit 10)

A22

SA9

System address bus (bit 9)

A23

SA8

System address bus (bit 8)

A24

SA7

System address bus (bit 7)

A25

SA6

System address bus (bit 6)

A26

SA5

System address bus (bit 5)

A27

SA4

System address bus (bit 4)

A28

SA3

System address bus (bit 3)

A29

SA2

System address bus (bit 2)

A30

SA1

System address bus (bit 1)

A31

SA0

System address bus (bit 0)

B1

GND

Ground

B2

RESET

ISA bus reset

B3

+5V DC

+5 Volts DC

B4

IRQ9

Interrupt request 9

B5

-5V DC

-5 Volts DC

B6

DRQ2

DMA request for channel 2

B7

-12V DC

-12 volts DC

B8

NOWS*

No wait state

B9

+12V DC

+12 volts DC

B10

GND

Ground

B11

SMWTC*

System memory write command

B12

SMRDC*

System memory read command

B13

IOWC*

I/O write command

B14

IORC*

I/O read command

B15

DACK3*

DMA acknowledge for channel 3

B16

DRQ3

DMA request for channel 3

B17

DACK1*

DMA acknowledge for channel 1

B18

DRQ1

DMA request for channel 1

B19

REFRESH*

Refresh

B20

BCLK

Bus clock (8.33 MHz)

B21

IRQ7

Interrupt request 7

B22

IRQ6

Interrupt request 6

B23

IRQ5

Interrupt request 5

B24

IRQ4

Interrupt request 4

B25

IRQ3

Interrupt request 3

B26

DACK2*

DMA Acknowledge for channel 2

B27

TC

Transfer complete

B28

BALE

Buffered address latch enable

B29

+5V DC

+5 volts DC

B30

OSC

Oscillator (8.33 mhz)

B31

GND

Ground

C1

SBHE*

System bus high enable

C2

LA23

Latch address bus (bit 23)

C3

LA22

Latch address bus (bit 22)

C4

LA21

Latch address bus (bit 21)

C5

LA20

Latch address bus (bit 20)

C6

LA19

Latch address bus (bit 19)

C7

LA18

Latch address bus (bit 18)

C8

LA17

Latch address bus (bit 17)

C9

MRDC*

Memory read command

C10

MWTC*

Memory write command

C11

SD8

System data bus (bit 8)

C12

SD9

System data bus (bit 9)

C13

SD10

System data bus (bit 10)

C14

SD11

System data bus (bit 11)

C15

SD12

System data bus (bit 12)

C16

SD13

System data bus (bit 13)

C17

SD14

System data bus (bit 14)

C18

SD15

System data bus (bit 15)

D1

M16*

Memory size 16

D2

IO16*

I/O size 16

D3

IRQ10

Interrupt request 10

D4

IRQ11

Interrupt request 11

D5

IRQ12

Interrupt request 12

D6

IRQ15

Interrupt request 15

D7

IRQ14

Interrupt request 14

D8

DACK0*

DMA acknowledge for channel 0

D9

DRQ0

DMA request for channel 0

D10

DACK5*

DMA acknowledge for channel 5

D11

DRQ5

DMA request for channel 5

D12

DACK6*

DMA acknowledge for channel 6

D13

DRQ6

DMA request for channel 6

D14

DACK7*

DMA acknowledge for channel 7

D15

DRQ7

DMA request for channel 7

D16

+5V DC

+5 volts DC

D17

MASTER16*

16-bit ISA master

D18

GND

Ground